View HV311LG-G_8658461.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv311 features 10 to 90v operation, positive or negative supply uv/ov lock out & power-on-reset circuit breaker 100ms startup timer automatic retry or latched operation low power, 400a sleep mode active low power good 8-lead soic package applications 48v central of?ce switching 24v cellular and ?xed wireless systems 24v pbx systems line cards 48v powered ethernet for voip distributed power systems power supply control 48v storage networks electronic circuit breaker ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex hv311 hot swap controller provides inrush current limiting and other power supply support functions for hot swap equipment. current limiting is provided by control of an external mosfet which is placed in the return line of the power supply connection. placement in the return allows use of an n-channel mosfet without the need for high side driving. an internal clamp at the gate pin activates when full bias for the hv311 is not available, thus keeping the mosfet in the off-state during the initial insertion phase. as soon as adequate bias is available for the main control circuits, the uv (undervoltage) and ov (overvoltage) pins check for normal operating voltage on the power supply input. once normal operating voltage is present, the gate voltage for the external mosfet ramps up at a constant rate. the rate is controlled by the value of an external capacitor placed at the ramp pin. at some point the external mosfet channel is enhanced, allowing power supply current to ?ow, thereby energizing downstream power supply capacitors. during the gate ramp up the power supply current is monitored with the aid of an external sense resistor which forces reduction in the ramp rate when the power supply current reaches a set limit. the limit is set by the value of the external sense resistor and the threshold of the current sense ampli?er (50mv). once inrush current subsides, the gate voltage resumes its rise to the output voltage of an internal regulator v reg , with an output voltage ranging from 8.5 to 12v. when gate is within 1.2v of v reg , gate is pulled high to v reg with an internal switch, the open-drain pwrgd pin pulls low, and the hv311 enters a low power mode. the hv311 includes a start-up timer and a circuit breaker function to protect the mosfet from excessive power dissipation. the start-up timer trips when the start-up phase exceeds 100ms. the circuit breaker trips at double the current limit threshold (100mv). upon tripping of either the start-up timer or the circuit breaker the mosfet is turned off, and the pwrgd pin becomes high impedance. thereafter, a programmable automatic retry timer allows the mosfet to cool down before resetting and restarting. the automatic retry can be disabled by adding an external resistor at the ramp pin (about 2.5m, see applications section). typical application circuit hot swap controller v dd uv ov vee sense gate -48v r4 12.5m r1 487k r2 6.81k r3 9.76k q1 irf530 c load +5.0v hv311 8 32 5 4 com dc/dc pwm converter 1 gnd notes: 1. undervoltage threshold (uv) set to 35v. 2. overvoltage threshold (ov) set to 65v. 3. startup current set to 4a.4. circuit breaker set to 8a. 5. 100ms max startup time. 6. automatic retry enabled. pwrgd enable 6 ramp 7 c1 10nf -48v downloaded from: http:///
2 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com ordering information device package options 8-lead soic (narrow body) 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch hv311 HV311LG-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v dd (referenced to v ee ) -0.3v to +100v v pwrgd (referenced to v ee ) -0.3v to +100v v uv and v ov (referenced to v ee ) -0.3v to +12v operating ambient temperature, t j -40c to +85c operating junction temperature, t j -40c to +125c storage temperature range, t s -65c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin con?guration electrical characteristics (-40 o c to +85c unless otherwise speci?ed, all voltages are referenced to v ee ) 8-lead soic (lg) 8-lead soic (lg) product marking y = last digit of year sealed ww = week sealed l = lot number = green packaging y w w hv311 l l l l 12 3 4 87 6 5 pwrgd ov uv vee vdd ramp gate sense sym parameter min typ max units conditions supply v dd supply voltage 10 - 90 v --- i dd supply current - 600 700 a v dd = 48v, mode = limiting standby mode supply current - 400 450 a v dd = 48v, mode = standby ov and uv comparators v rth rising threshold - 1.26 - v low to high transition v fth falling threshold - 1.16 - v high to low transition v hys hysteresis - 100 - mv --- i input current 1 - - 1.0 na v uv = 1.9v current limit v cl current limit threshold voltage 40 50 60 mv v uv = 1.9v, v ov = 0.5v v cb circuit breaker threshold voltage 80 100 120 mv v uv = 1.9v, v ov = 0.5v notes: guaranteed by design. 1. downloaded from: http:///
3 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com notes: this timing depends on the threshold voltage of the external n-channel mosfet. the higher its thresh old is, the longer this timing. this voltage depends on the characteristics of the external n-channel mosfet. v th = 3.0v for an irf530. irf530 is a registered trademark of international recti?er. 1.2. 3. sym parameter min typ max units conditions gate drive output v gate maximum gate drive voltage 8.5 10 12 v v uv = 1.9v, v ov =0.5v i gateup gate drive pull-up current 500 - - a v uv = 1.9v, v ov = 0.5v i gatedown gate drive pull-down current 40 - - ma v uv = 0v, v ov = 0.5v ramp timing control (test conditions: c load = 100f, c ramp = 10nf, v uv = 1.9v, v ov = 0.5v, external mosfet is irf530 3 ) i ramp ramp pin output current - 10 - a v sense = 0v t por time from uv to gate turn on 1 2.0 - - ms --- t rise time from gate turn on to v sense limit 400 - - s --- t limit duration of current limit mode - 5.0 - ms --- t pwrgd time from current limit to pwrgd - 5.0 - ms --- v ramp voltage on ramp pin in current limit mode 2 - 3.6 - v --- t startlimit start up time limit 80 100 120 ms --- t cbtrip circuit breaker delay time 2.0 - 5.0 s may be extended by external rc circuit t auto automatic restart delay time 12 - - s --- power good output v pwrgd(hi) power good pin breakdown voltage 90 - - v pwrgd is high v pwrgd(lo) power good pin output low voltage - 0.5 0.8 v i pwrgd = 1.0ma, pwrgd is low dynamic characteristics t gatehlov ov delay - - 500 ns --- t gatehluv uv delay - - 500 ns --- electrical characteristics (-40 o c to +85c unless otherwise speci?ed, all voltages are referenced to v ee ) downloaded from: http:///
4 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com functional block diagram the hv311 provides control over the power supply cur- rent on systems where circuit cards are inserted into live backplanes. such systems can frequently be found in the telecom, data networking and computing industry. the de- vice provides means of limiting the power supply current af- ter contact with the live backplane is made, thereby protect- ing card and backplane connectors and reducing the voltage disturbance on the backplanes power supply. additional protection is provided in the form of a circuit breaker function and a start-up time limiter, both for protection of the external mosfet and the system as a whole. start-up sequence after ?rst contact is made with the backplane, the hv311 tries to establish an internal bias supply of 10v. during this time, gate and ramp are positively held low by circuitry that can operate with partial supply voltage, and pwrgd is in a high impedance state. when the internal bias supply is in regulation, the undervoltage (uv) and overvoltage (ov) comparators start monitoring the external power supply. external resistor dividers at uv and ov pin set the window for normal operating supply voltage. these may be two individual dividers, or a single divider with two taps, as shown in the application diagrams. once the power supply voltage is within normal operating range, a 10a internal source turns on to charge an external capacitor at the ramp pin. the voltage at the gate output follows the ramp pin voltage with an offset of about 2.5v for control of the external mosfet. power supply current starts to ?ow once the gate voltage reaches the mosfet threshold voltage, which is typically in the 2.0 to 4.0v range. the current sense ampli?er at the sense pin reduces the ramp charging current in propor- tion to the supply current, thereby slowing the voltage rise at ramp, and thus the rise of the gate voltage. at a sense voltage of 50mv the ramp current is reduced to zero, and the ramp and gate voltages stop rising, thereby prevent- ing a further rise in the power supply current. v bg c c c uv ov logic regulator & por vin pwrgd ~9.8v ramp 2v bg gm sense 10a transconductor d i sa b l e p u ll h i g h v reg 1 : 2 buffer mirror gate 5k 5k? latch highsleep clamp mechanism transconductor uvlo vee functional description downloaded from: http:///
5 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com once external power supply capacitors are charged, the power supply current subsides, and the ramp current in- creases again to its maximum value of 10a. the ramp and gate voltages resume their rise. when the ramp volt- age is within 1.2v of the internal supply, then gate is con- nected to the internal supply, and the open-drain pwrgd pin is pulled low, marking the end of the start-up. if the start-up sequence is not ?nished within 100ms, then the internal start-up timer causes a reset of the ramp and gate voltage to 0v, and the automatic retry timer is started to allow the mosfet to cool off. after the retry delay a new startup sequence is initiated if the power supply voltage is within the normal operating range, as determined by the uv and ov comparators. the circuit breaker monitors the sense ampli?er for the pres- ence of an overcurrent condition at all times. the overcur- rent threshold is set at twice the maximum inrush current threshold. should overcurrent occur, then ramp and gate are brought to zero, pwrgd returs to high impedance, and the automatic retry timer is started. the automatic retry timer can be disabled by attachment of an additional resistor at the ramp pin if a latched shutdown is desired. a further reduction in the ramp rate of the ramp and gate voltages can be attained by connection of a feedback ca- pacitor from the drain node to the ramp pin. during startup the drain voltage drops at a rate proportional to the inrush current. this falling voltage waveform can be used to fur- ther reduce the current that ?ows onto the ramp capacitor, thereby reducing the maximum inrush current. setting up the uv and ov comparators the following example shows how the resistors for the threshold setting divider can be determined. the procedure applies to the (r1, r2, r3) divider having two taps as shown on the typical applications diagram. the following procedure bases the selection of the divider resistors on speci?cation of the shutdown / disable voltages. a similar procedure can be devised that bases selection on speci?cation of the enable voltages. lets assume the following: nominal divider current draw i nom = 100a, nominal power supply voltage v nom = 50v, overvoltage shutdown voltage v ovs = 65v, undervoltage shutdown voltage v uvs = 35v, negligible (uv, ov) comparator input currents, comparator rising threshold v rth = 1.26v comparator falling threshold v fth = 1.16v the following applies: r 123 = (r 1 + r 2 + r 3 ) r 123 = v nom / i nom r 123 = 500k r 3 follows from the ov shutdown voltage: df ov = r 3 / r 123 v rth = v ovs df ov r 3 = r 123 v rth / v ovs r 3 = 9.692k (97.6k 1%) ?? ? ? ? ? ? ? ? ? ? ? ? ? r 2 follows from the uv shutdown voltage: df uv = (r 2 + r 3 ) / r 123 v fth = v uvs df uv r 2 + r 3 = r 123 v fth / v uvs r2 = 6.879k (6.81k 1%) and: r1 = 483.429k (487k 1%) now the upper and lower enable voltages can be deter- mined: lower enable voltage v len upper enable voltage v uen v rth = df uv v len v fth = df ov v uen v len = 38.0v v uen = 59.8v programming maximum inrush current and circuit breaker current the values of the current limit threshold voltage v cl and the external current sense resistor r cs determine the maximum power supply current during startup i max (the maximum in- rush current). similarly the circuit breaker trip current i cb is determined by the values of the circuit breaker threshold voltage v cb and the value of r cs . ?? ? ? ? ? ? ? ? ? ? functional description (cont.) design information downloaded from: http:///
6 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com a numerical example: v cl = 50mv v cb = 100mv r cs = 10m i max r cs = v cl i cb r cs = v cb i max = 5.0a i cb = 10a timing the ?gure shows the sequence of events during startup and associated timing characteristics. the following is a dis- cussion of timing values assuming the following component values: c ramp = 10nf c load = 100f v vdd = 48v mosfet = irf530 v gs(th) = 3.0v g m = 7.4s r cs = 50m (i max = 1.0a) ?? ? ? ? ? ? a number of false starts may be caused by contact bounce at the card edge. the startup begins when v vin rises through the lower enable voltage v len , whose level is programmed at the uv comparator. t start during this time the ramp voltage rises steadily as the 10a current source charges capacitor c ramp . the voltage at the gate pin starts to follow the ramp pin voltage when v ramp reaches a ?xed offset voltage v ofs of about 1.2v after a de- lay indicated as t start in the ?gure. t start i ramp = v ofs c ramp t start = (1.2)(10n)/(10) t start = 1.2ms t th this time interval is associated with the rise of the gate voltage from zero to the gate threshold voltage of the exter- nal mosfet. t th i ramp = v gs(th) c ramp t th = (3)(10n)/(10) t start = 3.0ms t rise during this time period the drain current rises more or less exponentially to the maximum inrush current i max . as current rises from zero, the ramp current is reduced by the action of the current sense ampli?er, hence the more or less expo- nential current rise. t rise is here de?ned as the time to reach 90% of i max . 90% rise corresponds to 2.3i ramp = c ramp v gs i max g m v gs t rise 2.3(c ramp i max ) / (i ramp g m ) t rise (2.3)(10n)(1)/(10)(7.4) = 0.3ms t lim during this time period the external load capacitor is charged at i max . i max t lim = c load v vdd t lim = (100)(48) / (1) t lim = 4.8ms t pwrgd final rise of gate voltage to v reg minus about 1.2v. i ramp t pwrgd = c ramp (v reg C (1.2v + v gs(th) + v gs )) t pwrgd = (10n)(10 C (1.2 + 3 + 1/7.4)/(10) t pwrgd = 4.3ms ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? design information (cont.) gnd -48v v in i in t start contact bounce i lim pwrgd v uvl t rise t pwrgd v gate initialization limiting full on v gate v out t lim t th v ramp v ramp v gate inactive active v out v in v gs(th) v gs(lim) v ee t por 90% downloaded from: http:///
7 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com startup timer the startup timer limits the startup to 100ms. should there be an overload or short circuit during startup, then the exter- nal pass transistor will carry current for no more than 100ms. upon tripping of the timer the ramp and gate voltages reset to zero, and the autoretry timer starts if enabled. circuit breaker the circuit breaker trips in less than 5.0s when the voltage across the sense resistor reaches 100mv. upon tripping of the circuit breaker the ramp and gate voltages reset to zero, and the autoretry timer starts if enabled. autoretry timer the retry interval is determined by charging and discharg- ing the c ramp capacitor 256 times. one cycle corresponds to charging of c ramp to 8.0v with a current of 2.5a, and subse- quent discharging to zero with a current of 2.5a. hence: i charge t cycle = c ramp 2 v t cycle = (10n)(2)(8)/(2.5) t cycle = 64ms t autoretry = (256)(64m) t autoretry = 16.4s the autoretry timer can be disabled by adding a resistor at the ramp pin. a resistor which keeps the ramp voltage from rising to 8.0v will keep the timer from counting. this can accomplished by adding a resistor at the ramp pin with a value of about 2.5m. note that this resistor forms an ad- ditional load during the startup, thereby causing the time in- tervals to increase somewhat. ?? ? ? ? kelvin connections in order to make an accurate measurement of power supply current it is advisable to make use of kelvin connections. the idea is to not incur voltage drops in the sense leads due to the main power supply current. see diagram below. paralleling external mosfets equal current sharing may not be achievable due to the tol- erance issues with the threshold voltage and gain charac- teristics of the mosfets. paralleling of devices is not rec- ommended. the issues with paralleling can be alleviated by using resistor ballasting. for this application the hv311 with active low pwrgd is recommended where the pwrgd pins of multiple hot swap circuits can be connected in a wired or con?guration. to negative terminal of power source to source of mosfet to v ee pin sense resistor to sense pin downloaded from: http:///
8 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com vdd uv ov vee sense gate ramp hv311 -48v r4 12.5m? r1 487k? r2 6.81k? r3 9.76k? q1 irf530 c load +5.0v 8 32 com 1 gnd c1 10nf + - dc/dc pwm converter pwrgd enable 5 7 4 6 vdd uv ov vee sense gate ramp hv311 pwrgd -48v cload +5.0v 8 32 5 7 4 com 1 gnd + - dc/dc pwm converter enable r4 12.5m? r1 487k? r2 6.81k? r3 9.76k? q1 irf530 c1 10nf 6 application circuit 1application circuit 2 note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . pwrgd output many dc/dc pwm converters reference their enable inputs to the negative input terminal. if the enabl e input is active low then the hv311 can be directly connected as shown below (application circuit 1) since the open drain pwrgd out- put is in a high-z state until the external mosfet is fully turned on and the potential on the negat ive input of the converter is essentially the same as the vee pin of the hv311. however, if the dc/dc pwm converter with the enable input circuit con?guration was active high, then the apparent choice of the hv311 would result in the creation of a current path through the protective diode clam p of the enable input and the pwrgd output mosfet of the hv311. for this situation the hv311 should be used as shown below . downloaded from: http:///
9 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 3application circuit 4 note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . -48v c load +5v 8 32 com 1 gnd optocoupler r4 12.5mw r1 487k? r2 6.81k? r3 9.76k? q1 irf530 c1 10nf 5 7 4 6 dc/dc pwm converter enable r load vdd uv ov vee sense gate ramp hv311 pwrgd -48v c load +5.0v 8 32 com 1 gnd optocoupler r4 60m? r1 487k? r2 6.81k? r3 9.76k? q1 irf530 c1 10nf 5 7 4 6 dc/dc pwm converter vdd uv ov vee sense gate ramp hv311 pwrgd enable in some applications the pwrgd signal is used to activate load circuitry on the isolated output side of the dc/dc pwm converter. in this situation an optocoupler is needed to provide the required isolation as shown bel ow. when the details of the load enable circuitry is not known, using an optocoupler always provides a s afe solution. downloaded from: http:///
10 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 5application circuit 6 note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . -48v r4 12.5m? r1 487k? r2 6.81k? r3 9.76k? q1 irf530 c load +5.0v 8 32 5 7 4 com 1 gnd c110nf c2 6 dc/dc pwm converter vdd uv ov vee sense gate ramp hv311 pwrgd enable -48v r5 12.5m r1 475k r2 16.2k r3 511k q1 irf530 c load +5.0v 8 32 5 7 4 com 1 gnd c110nf c2 r4 10k dc/dc pwm converter 6 vdd uv ov vee sense gate ramp hv311 pwrgd enable filtering voltage spikes on input supply in some systems over voltage spikes of very short duration may exist. for these systems a small capa citor may be added from the ov pin to the vee pin to ?lter the voltage spikes. unfortunately this will also cause some delay in responding to uv conditions. if this uv delay is no t acceptable, then sepa- rate resistor dividers can be provided for ov and uv with a capacitor connected from ov pin to the v ee pin. downloaded from: http:///
11 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 7application circuit 8 note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . -48 v r412.5m r1 487k r2 6.81k r3 9.76k q1irf530 c load +5.0v 8 32 5 7 4 com 1 gnd c1 10nf longpin shortpin longpin gnd 6 dc/dc pwm converter vdd uv ov vee sense gate ramp hv311 pwrgd enable -48v irf530 r5 r1 475k r2 16.2k r3 511k q1 c load +5.0v 8 32 5 7 4 com 1 gnd c110nf 12.5m r410k longpin longpin shortpin gnd 6 dc/dc pwm converter vdd uv ov vee sense gate ramp hv311 pwrgd enable using short connector pin in some systems short connector pins are used to guarantee that the power pins are fully mated befor e the hot swap control circuit is enabled. for these systems the positive (vdd) end of the r1, r2, and r3 resistor divider should be connected to if separate resistor dividers are used for ov and uv, then only the positive (vdd) end of the uv res istor divider should be connected to the short pin. downloaded from: http:///
12 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 9application circuit 10 -48 v r5 12.5m r1 475k r2 16.2k r3 511k q1 irf530 c load +5.0v 8 32 5 7 4 com 1 gnd c110nf r4 10k -48v 6.2v longpin shortpin longpin dc/dc pwm converter 6 vdd uv ov vee sense gate ramp hv311 pwrgd enable note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . -48 v r4 12.5m r1 487k r2 6.81k r3 9.76k q1 irf530 c load +5.0v 8 32 5 4 com 1 gnd c110nf longpin shortpin longpin -48v 6.2v dc/dc pwm converter vdd uv ov vee sense gate ramp hv311 pwrgd enable 7 6 if a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully mated before the hot swap control circuit is enabled and uses separate resistor dividers for uv and ov, then a 6.2 to 10v zener diode must be connected from the ov pin to the vee pin and only the ov divider should be conne cted to the short pin. if a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully mated before the hot swap control circuit is enabled and uses separate resistor dividers for uv and ov, then a 6.2v to 10v zener diode must be connected from the ov pin to the vee pin and only the ov divider should be conne cted to the short pin. downloaded from: http:///
13 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 12 note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . application circuit 11 -48v r4 12.5m r1 487k r2 6.81k r3 9.76k q1 irf530 +5v 8 32 5 7 4 com 1 gnd c1 10nf d1 6 dc/dc pwm converter c load vdd uv ov vee sense gate ramp hv311 pwrgd enable -48v r5 12.5m r1 475k r2 16.2k r3 511k q1 irf530 +5v 8 32 5 7 4 com 1 gnd c110nf r4 10k r6 dc/dc pwm converter 6 c load vdd uv ov vee sense gate ramp hv311 pwrgd enable increasing under voltage hysteresis if the internally ?xed under voltage hysteresis is insuf?cient for a particular system application, then it may be increased by using separate resistor dividers for ov and uv and providing a resistor feedback path from the gate pin to the uv pin.reverse polarity protection the uv and ov pins are protected against reverse polarity input supplies by internal clamping diodes and the fault currents are suf?ciently limited by the impedance of the external resistor divider, however, a low current di ode with a 100v breakdown rating must be inserted in series with the vdd pin. this method (shown in application circuit 12 ) will protect the hot swap control circuit however, due to the intrinsic diode in the external mosfet, the load will not be protected from reverse polarity voltages. downloaded from: http:///
14 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 13note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . - 48v +5v 8 3 2 com 1 gnd notes : 1. undervoltage shutdown (uv) set to 35v. 2. overvoltage shutdown (ov) set to 65v. 3. current limit set to 0.83a. -48v r4 60m r1 487k r2 6.81k r3 9.76k q1 irf530 8 32 5 7 4 1 gnd c110nf d1 d1 d2 d2 ps1 ps2 6 r1 487k r2 6.81k r3 9.76k 5 7 4 6 r4 60m q1 irf530 c110nf dc/dc pwm converter c load vdd uv ov vee sense gate ramp hv311 vdd uv ov vee sense gate ramp hv311 pwrgd pwrgd enable redundant supplies many systems use redundant primary power supplies or battery backup. when redundant ac powered sourc es are used they are generally diode ored to the load on the hot terminal. for these systems, the use of indepe ndent hot swap control- lers is recommended with the diode oring provided after the hot swap controllers. the hv311 is idea lly suited for such ap- plications since two or more active low pwrgd signals can be connected to a single active low enable pin, thus enabling the load as long as at least one primary power source is available. by adding low current 100v diode s in series with the vdd pins, full reverse polarity protection on either power source is also provided. downloaded from: http:///
15 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 14note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . +48v +5v 8 32 com 1 gnd r4 12.5m r1 487k r2 6.81k r3 9.76k q1 irf530 c1 10nf dc/dc pwm converter 5 7 4 6 c load vdd uv ov vee sense gate ramp hv311 pwrgd enable use with negative ground the hv311 may be used with many positive ground systems where dc/dc pwm converters have isolated out puts and their inputs need not be ground referenced. application circuit 15note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . -48v +5v 8 32 com 1 gnd c2 r5 dc/dc pwm converter r4 12.5m r1 487k r2 6.81k r3 9.76k q1 irf530 5 7 4 6 c load vdd uv ov vee sense gate ramp hv311 pwrgd enable extending circuit breaker delay connecting a resistor in series with the sense pin and a capacitor between the sense and vee pins as shown in the fol- lowing diagram may be used to extend the circuit breaker delay time beyond the 5s internally set de lay time. the time delay achievable by this method is limited since this application circuit 7 delay circuit will also effect the current control feedback loop and will result in a current overshoot during the external pass device turn on transition to current limit. if the time delay required for the circuit breaker causes excessive current overshoot during the tur n on transition then the following circuit may be used, where the rc ?lter is switched on after the completion of the current limit control function of the hot swap controller. downloaded from: http:///
16 hv311 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application circuit 16note: a capacitor may be needed to slow pwrgd dv/dt if gate oscillations are observed when v in is close to ov lo . -48v +5v 8 32 com 1 gnd enable dc/dc pwm converter 7 5 6 4 r1 487k r2 6.81k r3 9.76k r4 12.5m q1 irf530 2.5m c load vdd uv ov vee sense gate ramp hv311 pwrgd latched operations for those applications that need to disable the auto retry capability, the following circuit disable s the auto retry feature. pin # name description 1 pwrgd the power good output pin. pin is an open-drain output. connect to power module enable pins and the like with internal or external pull-up resistor(s). this open-drain pin is high impedance during the start-up phase, during fault, and automatic retry periods, and low otherwise. 2 ov the overvoltage input pin. input to the ov/uv window comparator. monitors the power supply voltage, for purpose of detecting the normal operating voltage condition. 3 uv the undervoltage input pin. input to the ov/uv window comparator. monitors the power supply voltage, for purpose of detecting the normal operating voltage condition. 4 vee the negative power supply pin. connect to the negative of the incoming power supply. 5 sense the current sense pin. connect the current sense resistor between the vee and sense pins. regulates the inrush current to 50mv equivalent. trips on over current at 100mv equivalent. 6 gate the gate output. connect to the gate of external mosfet. connect the source of the mosfet source to the vee pin. 7 ramp the ramp input pin. connect a capacitor between this pin and vee to control the ramp rate of the voltage at the gate pin during power-up. add a resistor of about 2.5m to disable the autoretry feature. 8 vdd the positive power supply pin. connect to the positive of the incoming power supply. pin description downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receive s an adequate product liability indemnification insuran ce agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for p ossible omissions and inaccuracies. circuitry and s pecifications are subject to change without notice. for the lates t product specifications refer to the supertex inc. website: http//www.supertex.com. ?2008 all rights reserved. unauthorized use or reproduct ion is prohibited. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com 17 hv311 (the package drawings in this data sheet may not re?ect the most current speci?cations. for the late st package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv311 a120808 8-lead soic (narrow body) package outline (lg) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch 1 8 seating plane gauge plane l l1 l2 e e1 d e b a a2 a1 seating plane a a top view side view view b view b 1 note 1 (index area d/2 x e1/2) view a-a h h note 1 symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 4.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation aa, issue e, sept. 2005. * this dimension is not speci?ed in the original jedec drawing. the value listed is for reference o nly. drawings are not to scale. supertex doc. #: dspd-8solgtg, version h101708. note: this chamfer feature is optional. a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1. downloaded from: http:///

▲Up To Search▲

Price & Availability of HV311LG-G

	To Download HV311LG-G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .